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Altera_Forum's avatar
Altera_Forum
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13 years ago

How are timing assignments set?

I have a signal which is very slow to change to the new value each clock cycle. Can I solve this problem with timing assignments? If so, how? I have a case statement similar to the one below: ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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Are b, and d* registers?

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b is a register. d is not.

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Quartus does have timing driven synthesis and fitting: you specify timing constraints and the software tries to optimize the design as much as needed until your constraints are met.

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So, how would I specify a timing constraint that would force c to change to d within, let's say, 5 ns of b changing?