How are timing assignments set?

How I imagine the synthesizer would implement this is with a multiplexer. Therefore, the combinational logic should be very simple. So, I don't understand why it takes so long to settle. I can't think of any other logic that would be faster.

What's stranger to me, however, is the amount of time it takes for c to even begin to change from dn to dn+1. It's about 10 ns which means that the signal b must be taking a route of about 3 metres. 3 metres in a chip that is about a square inch in size! Unless for some reason the signal does not travel at the speed of light.

This last problem could be solved by somehow forcing the fitter to choose a shorter route. I had guessed that this is what timing assignments did. But are you saying that timing assignments cannot be used to solve my problem? Your sole suggestion seems like something that would simply tell the fitter to make all routes shorter rather than singling out a single problematic path.