when i synthesis & fit my design, hold time violation is reported at my output port in fast model timing analysis. the fpga was connected with some slow device, which requires a relative large hold time, as 10ns. it is always compiled with negative slack, about -3~-7ns. i think i can add some delay on the output of data, but i did not find the way to route manually btw: i am using cyclone ii which can only set the max 6ns delay by "Delay from Output Register to Output Pin" by assignment editor. and it is useless also.

It sounds like the constraints are setup, which is good. A few things to check: 1) Assignments -> Settings -> Fitter. Optimize Hold Timing should be on for at least I/O(All Paths will work too) and make sure multi-corner optimization is checked. I don't think this latter is on by default in many versions. 2) Double check the setup slack at the slow corner. To add ~10ns in the Fast is probably adding 20-25ns in the slow corner, depending on speed grade. If that's tight on setup timing, the fitter is just trying to split the difference. 3) Make sure there is no Fast Output Register = On assignment. (You would have manually done this, so unlikely). This would force it into the I/O, and as you said, the delay chain can't be large enough to meet timing. 4) A location assignment for the register far away from the I/O should do the trick, although you shouldn't have to do this. Highlight the register in the TimeQuest report, Locate -> Assignment Editor so the register name shows up in the To column, Location as the assignment, and do something like LAB_X1_Y1, for example, to put it in the bottom left corner. 5) A 10ns hold requirement is quite large. Usually when I've seen stuff like that, it's met by sending data out on the falling edge, which adds a half-cycle delay that is PVT invariant. Just an idea.

is there any way to insert some LCELL as delay chains?

You can manually instantiate them. lcell is the name, and I believe in and out are the ports. (I think in VHDL a_in and a_out are the ports, since in and out are keywords). Naturally without hand-placing them, you can get a lot of variance. If you have timing constraints that require a positive hold, check that Assignments -> Settings -> Fitter has Optimize Hold Timing set to All Paths and Optimize Multi-Corner is checked. This tells the router to add delays to try and meet hold requirements. As a test, I took a FF->FF in Cyclone 3 and added a 20ns hold requirement. The router was able to meet this by routing around the chip almost twice. (Note that it failed at first because I had a 30ns setup requirement. Adding 20ns in the fast corner is ~40ns in the slow corner, so I had given it impossible constraints. By making the setup relationship 50ns or so(I don't remember), the hold could be met.)

i believe fitter would work in many situation. i checked the setup time for my design, it remains about ~20ns as slack in slow model, which means that fitter have sufficient time slack for hold time. but in realistic it is not. it is odd&#12290;

I am a bit worried about a device with +10ns tH. are you sure? or is it -10ns with tSU close to it but +ve.

hold time violation | Altera Community

20 Replies

Altera_Forum
Honored Contributor
15 years ago
It sounds like the constraints are setup, which is good. A few things to check:
1) Assignments -> Settings -> Fitter. Optimize Hold Timing should be on for at least I/O(All Paths will work too) and make sure multi-corner optimization is checked. I don't think this latter is on by default in many versions.
2) Double check the setup slack at the slow corner. To add ~10ns in the Fast is probably adding 20-25ns in the slow corner, depending on speed grade. If that's tight on setup timing, the fitter is just trying to split the difference.
3) Make sure there is no Fast Output Register = On assignment. (You would have manually done this, so unlikely). This would force it into the I/O, and as you said, the delay chain can't be large enough to meet timing.
4) A location assignment for the register far away from the I/O should do the trick, although you shouldn't have to do this. Highlight the register in the TimeQuest report, Locate -> Assignment Editor so the register name shows up in the To column, Location as the assignment, and do something like LAB_X1_Y1, for example, to put it in the bottom left corner.
5) A 10ns hold requirement is quite large. Usually when I've seen stuff like that, it's met by sending data out on the falling edge, which adds a half-cycle delay that is PVT invariant. Just an idea.
Altera_Forum
Honored Contributor
15 years ago
is there any way to insert some LCELL as delay chains?
Altera_Forum
Honored Contributor
15 years ago
You can manually instantiate them. lcell is the name, and I believe in and out are the ports. (I think in VHDL a_in and a_out are the ports, since in and out are keywords). Naturally without hand-placing them, you can get a lot of variance. If you have timing constraints that require a positive hold, check that Assignments -> Settings -> Fitter has Optimize Hold Timing set to All Paths and Optimize Multi-Corner is checked. This tells the router to add delays to try and meet hold requirements. As a test, I took a FF->FF in Cyclone 3 and added a 20ns hold requirement. The router was able to meet this by routing around the chip almost twice. (Note that it failed at first because I had a 30ns setup requirement. Adding 20ns in the fast corner is ~40ns in the slow corner, so I had given it impossible constraints. By making the setup relationship 50ns or so(I don't remember), the hold could be met.)
Altera_Forum
Honored Contributor
15 years ago
i believe fitter would work in many situation.
i checked the setup time for my design, it remains about ~20ns as slack in slow model, which means that fitter have sufficient time slack for hold time. but in realistic it is not.
it is odd。
Altera_Forum
Honored Contributor
15 years ago
I am a bit worried about a device with +10ns tH. are you sure? or is it -10ns with tSU close to it but +ve.
Altera_Forum
Honored Contributor
15 years ago
--- Quote Start ---
I am a bit worried about a device with +10ns tH. are you sure? or is it -10ns with tSU close to it but +ve.
--- Quote End ---

it is a phy chip compliant with 10/100BASE-T.
the hold time comes from the datasheet.
Altera_Forum
Honored Contributor
15 years ago
How much is the device tSU?

For tH of + 10 ns, and if you are sending clock and data together from fpga then you need to delay the clock relative to data. Alternatively, send the clock inverted, inversion may solve the tH problem since it implies half period clock delay.
Altera_Forum
Honored Contributor
15 years ago
10ns also.

ok, i will try that.
Altera_Forum
Honored Contributor
15 years ago
having tSU = 10 ns and tH = 10 ns gives a sampling window of 20 ns during which data should not change. The transition window is what is left of:
clk period - 20ns. I hope you have enough margin left.
Altera_Forum
Honored Contributor
15 years ago
the period is 40ns.
according to sta result, it would have 23ns slack for setup check, which, in my opinion, minus 10ns still have 13ns margin.

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hold time violation

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