entity counter is generic ( n : natural := 4; ); port ( clock : in std_logic; reset_n : in std_logic; q : out std_logic_vector(n-1 downto 0) ); end entity; architecture rtl of counter is signal value : std_logic_vector(n-1 downto 0); begin process(clock, reset_n) begin if (reset_n = ’0’) then value <= (others => ’0’); elsif ((clock’event) and (clock = ’1’)) then value <= value + 1; end if; end process; q <= value; end rtl;

This is a very simple piece of code: First the Entity "counter" is declared with a Generic "n" (Kind of Parameter used for the Instance-Generating) and three Ports "clock", "reset_n" and the only Output "Q" whith the variable width of "n". Then the Architecture: There is one Signal "value" (Wire for Verilog-Programmers) also with the variable width of "n". The PROCESS: The Process listenes to "clock" and "restet_n": If "reset_n" is '0' then all bits of "value" are cleared to '0'. If "reset_n" is not '0', then value is counted up by one if there is a rising edge on "clock". The setting of the Output: The Output "Q" is set to the value of "value" asynchronously. You can also do the staight way and increment "Q" in the Process, but it is recommended not to use Outputs in a Process because you can not read from them. For Example if you increment "value" you can use this Signal in another Process and read it out. If you increment "Q" instead, you cannot read "Q" in another Process because Output-Ports are not readable.

It appears to be a non-standard counter (unless it's VHDL 2008). But you missed out the library inclusions, so would not compile at all.

thanks!! and for example, an 8-bit counter can be specied as?? eight bit:counter generic map( n => 8 ) port map eight bit ( clock , resetn , Q) ; i want create a modulo-k counter by modifying the design of an 8-bit counter to contain an additional parameter, the counter should count from 0 to k-1 and when the counter reaches the value k -1 the value that follows should be 0.

I'm interested create a modulo-k counter by modifying the design of an 8-bit counter to contain an additional parameter

hi! Understanding a coding (counter), help

16 Replies

Altera_Forum
Honored Contributor
11 years ago
It sounds like a homework assignment. It looks like code to me - why not try writing a testbench and simulating it?
Altera_Forum
Honored Contributor
11 years ago
Apparently you want to create a hierarchical design by instantiating the component counter in a top entity. But you don't write a separate entity, instead a second architecture inside the entity counter. This doesn't work.
Altera_Forum
Honored Contributor
11 years ago
Hi, On the 2nd part your are *completely* wrong : you can't use the same entity in the description of THIS entity, It is equivalent to saying "A car is made with a car",
I recommand port mapping by names, not by position, some thing like this
my_counter : entity counter generic map ( n => 8, k => 4) port map ( clock => KEY(1), reset_n => KEY(0), Q => Q_int, SW => ???, KEY => ???, LEDR => ??? ); LEDR <= Q_int;

I think that you only have to modify the "rtl" architecture, that what you have done.
Altera_Forum
Honored Contributor
11 years ago
HI!! help please...Why it gives me this error? I want to put a function of k n

library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use ieee.numeric_std.all;

entity contador is
generic (
k : natural:= 8;
n : natural:= LOG2(k+1)--> error (10482): vhdl error at contador.vhd(12): object "log2" is used but not declared

);

port
(
clock: in std_logic;
reset_n: in std_logic;
Q : out std_logic_vector (n-1 downto 0)

);

end contador;

architecture rtl of contador is
signal clock,reset_n: std_logic;
signal Q_int: std_logic_vector(n-1 downto 0);
begin

PROCESS(clock, reset_n)
begin

if (reset_n = '0') then

Q_int<= (others => '0');

elsif ((clock'event) and (clock = '1')) then
if (Q_int<k) then

Q_int <= Q_int + 1;
else

Q_int<= (others => '0');

end if;
end if;
end process;
Q <= Q_int;
end rtl;
Altera_Forum
Honored Contributor
11 years ago
You have no log2 function included - you will need to write one and add it to a package. You will also struggle because you cannot use other generics inside the generic region
Altera_Forum
Honored Contributor
11 years ago
moreover the generic 'k' is not used here. So you can delete it.
(and give to 'n' the number of bits.)

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hi! Understanding a coding (counter), help

16 Replies

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