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scabr8's avatar
scabr8
Icon for New Contributor rankNew Contributor
5 years ago

Hi, i am having this error and I don't know how to fix it, I have to finish this for today for my school and I do not know what to do. Error (10170): Verilog HDL syntax error at ctrl.v(170) near text: "assign"; expecting an operand.

ak6dn's avatar
ak6dn
Icon for Regular Contributor rankRegular Contributor
5 years ago

You have to supply the verilog source code line(s) that are being flagged or no one is going to be able to help you in any reasonable way. Just the error message(s) are not enough.