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Altera_Forum's avatar
Altera_Forum
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14 years ago

hey experienced members Plz help me?

My project is: design and test 4X4 bit unsigned multiplier using right shift add algorithm

With little knowledge about VHDL

One friend Kaz has helped me write the code.but I dont understand completely. Can you explain it to me?

here is the code that I get troubles:

architecture rtl of mult1 is

signal shift_reg1 : std_logic_vector(3 downto 0) := "0000";

signal shift_reg2 : std_logic_vector(7 downto 0) := x"00";

signal reg1 : std_logic_vector(7 downto 0);

signal opA : std_logic_vector(3 downto 0);

begin

R <= shift_reg2(0);

reg1(7 downto 3) <= std_logic_vector(resize(unsigned(OpA),5) + unsigned(shift_reg2(7 downto 4)));

reg1(2 downto 0) <= shift_reg2(3 downto 1);

what's the three signals shift-reg1,shift-reg2,reg1( they are the singals between?) what does shift-reg2(0) mean?

Is it nessecary to write :="0000" and :=x"00" at the signal shift-reg1,2

(My teacher dont write them in the signal declaration)

and the next code I almost don't understand ( other ways to write them easier to understand??).

I have added the diagram of the algorithm and the whole code( helped by Kaz) underneath.

Looking forward to hearing from you soon.;)

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    --- Quote Start ---

    architecture rtl of mult1 is

    signal shift_reg1 : std_logic_vector(3 downto 0) := "0000";

    signal shift_reg2 : std_logic_vector(7 downto 0) := x"00";

    signal reg1 : std_logic_vector(7 downto 0);

    signal opA : std_logic_vector(3 downto 0);

    begin

    R <= shift_reg2(0);

    reg1(7 downto 3) <= std_logic_vector(resize(unsigned(OpA),5) + unsigned(shift_reg2(7 downto 4)));

    reg1(2 downto 0) <= shift_reg2(3 downto 1);

    what's the three signals shift-reg1,shift-reg2,reg1( they are the singals between?)

    --- Quote End ---

    shift_reg1 corresponds to your 4 bit shift reg of multiplier.

    shift_reg2 is your second 8 bit register right at product output.

    reg1 is the other 8 bit register at top of your diagram

    --- Quote Start ---

    what does shift-reg2(0) mean?

    --- Quote End ---

    1st lsb of that register i.e. bit index 0

    --- Quote Start ---

    Is it nessecary to write :="0000" and :=x"00" at the signal shift-reg1,2

    --- Quote End ---

    no, but if you go to modelsim you will get some undefined initial values.

    --- Quote Start ---

    and the next code I almost don't understand ( other ways to write them easier to understand??).

    --- Quote End ---

    you can use an adder directly instead of addition statement. go to megawizard(tools menu) and let quartus create an adder then you need to connect as 4 bits , 4 bits inputs and 5 bits output.

    the shifting itself can be done through megawizard as well.