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architecture rtl of mult1 is
signal shift_reg1 : std_logic_vector(3 downto 0) := "0000";
signal shift_reg2 : std_logic_vector(7 downto 0) := x"00";
signal reg1 : std_logic_vector(7 downto 0);
signal opA : std_logic_vector(3 downto 0);
begin
R <= shift_reg2(0);
reg1(7 downto 3) <= std_logic_vector(resize(unsigned(OpA),5) + unsigned(shift_reg2(7 downto 4)));
reg1(2 downto 0) <= shift_reg2(3 downto 1);
what's the three signals shift-reg1,shift-reg2,reg1( they are the singals between?)
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shift_reg1 corresponds to your 4 bit shift reg of multiplier.
shift_reg2 is your second 8 bit register right at product output.
reg1 is the other 8 bit register at top of your diagram
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what does shift-reg2(0) mean?
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1st lsb of that register i.e. bit index 0
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Is it nessecary to write :="0000" and :=x"00" at the signal shift-reg1,2
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no, but if you go to modelsim you will get some undefined initial values.
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and the next code I almost don't understand ( other ways to write them easier to understand??).
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you can use an adder directly instead of addition statement. go to megawizard(tools menu) and let quartus create an adder then you need to connect as 4 bits , 4 bits inputs and 5 bits output.
the shifting itself can be done through megawizard as well.
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