Help with vhdl code

I did a quick compile on your top_level.vhd file, but this file is not complete. It is lacking the sub-module entities (like FSM_CHAINE and others). Which makes it quite impossible to appreciate where you got stuck.

thank you josyb for your reply

The forum is to help and give guidance, not to actually do your work/assignment ...

I have the solution is to use a mux between intra 4x4 and intra 16x16, but i'm not an expert with vhdl language, so if there is any help with the code i'll be so grateful :)

please try and do the assignment yourself, and then come back if you have problems. we will not do the work for you.

ok , i'll try to do prove my mux code. :)

Hello everyone I have tried to develop my mux, but I did not succeed to simulate my code it contains some errors. I do not know is that the code is right or wrong(for mux ) or it location is correct or not .

Could you define "it contains some errors" ?

I fixed the errors, the project compiles but it does not simulate if you can help me fix the code multiplexer, this is the code of mux added into CHAINE_TOP_LEVEL.vhd

--------------------------------mux1-----------------------------------------------
PROCESS (sel ,Mode)
    begin 
 case sel is 
        when '0' => Mode<= Mode_16;
            when '1'=> Mode<=Mode_4;
            when others => Mode <= Mode;
            end case;
        end process;
----------------------------------------------------------------------------------

Mode,  Mode_16,Mode_4 :in std_logic; 

sel :in std_logic; 

could you define "it does not simulate" ?

Mode,  Mode_16,Mode_4 :in std_logic;

when others => Mode <= Mode;

when others => Mode <= 'X';