Help with vhdl code

I fixed the errors, the project compiles but it does not simulate if you can help me fix the code multiplexer, this is the code of mux added into CHAINE_TOP_LEVEL.vhd

--------------------------------mux1-----------------------------------------------
PROCESS (sel ,Mode)
    begin 
 case sel is 
        when '0' => Mode<= Mode_16;
            when '1'=> Mode<=Mode_4;
            when others => Mode <= Mode;
            end case;
        end process;
----------------------------------------------------------------------------------

other problem when i put the variable Mode,Mode_16 and Mode_t4 on in like these

Mode,  Mode_16,Mode_4 :in std_logic; 

and the variable sel like these

sel :in std_logic; 

when i compile the project i get this error is

Error: C:/projet/CHAINE_TOP_LEVEL.vhd(110): Cannot drive signal 'mode' of mode IN.