Help with vhdl code

could you define "it does not simulate" ?

I'm sorry but if you don't give details about your problems we can't really help you.

On this line

Mode,  Mode_16,Mode_4 :in std_logic;

you define Mode as an input, but on in your process you are using it as an output. Try to define it as an output instead. You could hten get an error on this line:

when others => Mode <= Mode;

. I would personally use this instead

when others => Mode <= 'X';

as the case won't happen on real hardware, and using X will help you debug your system in case you are trying to use uninitialized signals.