Help with verilog testbench code

Am trying to solve a parking slot problem where an individual has 4 parking spaces outside of his/her apartment complex. this individual wants to know when two adjacent spaces are open as he/she does not want anyone to park next to their car. (normally, this person parks at the end of a large parking lot to avoid any scrapes or scratches). this individual proceeds to set up pressure switches in the parking spaces and has a logic indicator in their apartment building. they want one logic indicator to activate if two adjacent spaces become open, another logic indicator to activate if three adjacent spaces become open, a third if all spaces are open and a fourth if one space is open (in case they choose to risk it).

i am having problems with the testbench. it doesn't generate the desired output waves when i run it in modelsim. any help would be appreciated.

testbench

module parking_lot_tb;

wire p1 = 1'b0;

wire p2 = 1'b0;

wire p3 = 1'b0;

wire p4 = 1'b0;

wire a1;

wire a2;

wire a3;

wire a4;

reg clk;

parking_lot dut(

p1,

p2,

p3,

p4,

a1,

a2,

a3,

a4

);

initial begin

clk = 1;

end

always begin

assign# 100 p1 = ~( p1);

assign# 200 p2 = ~( p2);

assign# 300 p3 = ~( p3);

assign# 400 p4 = ~( p4);

end

initial

$monitor($stime,,clk,,a1,,a2,,a3,,a4,,);

endmodule

Main code:

module parking_lot(

p1,

p2,

p3,

p4,

a1,

a2,

a3,

a4

);

input p1;

input p2;

input p3;

input p4;

output a1;

output a2;

output a3;

output a4;

assign a1 = ( ( ( p1 | p2 ) | p3 ) | p4 );

assign a2 = ( ( ( p1 & p2 ) | ( p2 & p3 ) ) | ( p3 & p4 ) );

assign a3 = ( ( ( ( p1 & p2 ) & p3 ) & ~( p4) ) | ( ( p2 & p3 ) & p4 ) );

assign a4 = ( ( ( p1 & p2 ) & p3 ) & p4 );

endmodule