Help with verilog testbench code

I suggest you generate a 4-bit, registered, counter that generates the 16 different combinations of slot availability possible. Connect each bit of the counter to your p1-p4 module input signals.

There are several ways in which you could generate this stimulus - I'm not sure yours is one of them :oops:

You might try this:

module tb ();

reg [3:0] p;

integer i;

initial

begin

p = 0;

for (i=0; i<=15; i=i+1)

# 10 p = p + 1;

$stop();

end

// Connect up your module here...

endmodule

The 4-bit register 'p' gives you the four individual signals you need to stimulate you module with.