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Altera_Forum's avatar
Altera_Forum
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12 years ago

Help with constraining a parallel interface

Hi,

I am trying to constrain a parallel interface (PATA), but I am not sure what is the correct way to do it.

The interface is between a Cyclone V and an external chip:

https://www.alteraforum.com/forum/attachment.php?attachmentid=8280

The problem is constraining this interface when data is going from the FPGA to the external chip.

There are two relevant signals. The 16 bit Data (DD) and the strobe that is used by the external chip to sample the data (DSTROBE).

Data is sampled on both edges of the strobe which is toggling at maximum 25 MHz:

https://www.alteraforum.com/forum/attachment.php?attachmentid=8281

The setup and hold time requirements are 4.8 ns.

Both the strobe and data are generated by an internal 50 MHz clock. Data is clocked out on the falling edge and the strobe is clocked on the rising edge giving a 10 ns margin before and after the strobe edge. (and before any skew)

The strobe is generated by a state machine and not by a pll and is therefore not recognized as a clock.

https://www.alteraforum.com/forum/attachment.php?attachmentid=8279

I tried to create a clock constraint by using a constraint like this: 

create_generated_clock -name dstrobe_clk -source clk -divide_by 2 dstrobe

But I got a warning:

Warning (332088): No paths exist between clock target "dstrobe" of clock "dstrobe_clk" and its clock source. Assuming zero source clock latency.

Do I get this warning because of the muxes between the flip flop and the pin?

How do I create the clock constraint correctly?

If I manage to get the clock constraint correct I am planning to constrain the data like this (not accounting for board trace delay): 

set_output_delay -clock dstrobe_clk -max 4.8 
set_output_delay -clock dstrobe_clk -min -4.8 
set_output_delay -clock dstrobe_clk -max 4.8 -clock_fall  -add_delay
set_output_delay -clock dstrobe_clk -min -4.8 -clock_fall  -add_delay

Does this look correct to you?

Regards,

Jorgen

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    one way is to constrain strobe and data relative to their same one clk.

    if you set min delay for each to -9 and max to +9 then you are asking for transitions to occur from -9 to +9 from edges (a tight window of 2 ns).

    With data and strobe constrained for 2 ns relative to their edges you have ample room of about 8 ns for both setup and hold between strobe transition and data transition.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Dear jorkrohn,

    - Ensure your strobe is the output of a single register (ie, "dstrobe_reg"). Modify your FSM if needed.

    - Create a clock (ie, "dstrobe_reg_clk"), derived from "clk", targetted at the output of "dstrobe_reg".

    - Create a clock (ie, "dtrobe_clk"), derived from the former "dstrobe_reg_clk", targetted at the "dstrobe" output pin.

    The warning should now be gone and the the "dstrobe_clk" timing should now include all the internal delays.

    Constrain the output delays against the "dstrobe_clk".

    If your external device samples at the rising edge of dstrobe and it has a 4.8 ns tSU and tH, then all you need is.

    set_output_delay -clock dstrobe_clk -max 4.8 [get_ports {dd*}]

    set_output_delay -clock dstrobe_clk -min -4.8 [get_ports {dd*}]
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    --- Quote Start ---

    one way is to constrain strobe and data relative to their same one clk.

    if you set min delay for each to -9 and max to +9 then you are asking for transitions to occur from -9 to +9 from edges (a tight window of 2 ns).

    With data and strobe constrained for 2 ns relative to their edges you have ample room of about 8 ns for both setup and hold between strobe transition and data transition.

    --- Quote End ---

    Thanks for the suggestion. I tried this, but the requirement seems to be too strict. I also tried +-8 ns without any luck.

    --- Quote Start ---

    Dear jorkrohn,

    - Ensure your strobe is the output of a single register (ie, "dstrobe_reg"). Modify your FSM if needed.

    - Create a clock (ie, "dstrobe_reg_clk"), derived from "clk", targetted at the output of "dstrobe_reg".

    - Create a clock (ie, "dtrobe_clk"), derived from the former "dstrobe_reg_clk", targetted at the "dstrobe" output pin.

    The warning should now be gone and the the "dstrobe_clk" timing should now include all the internal delays.

    Constrain the output delays against the "dstrobe_clk".

    If your external device samples at the rising edge of dstrobe and it has a 4.8 ns tSU and tH, then all you need is.

    set_output_delay -clock dstrobe_clk -max 4.8 [get_ports {dd*}]

    set_output_delay -clock dstrobe_clk -min -4.8 [get_ports {dd*}]

    --- Quote End ---

    Thanks! Creating the clock constraint in two steps seems to work fine.