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one way is to constrain strobe and data relative to their same one clk.
if you set min delay for each to -9 and max to +9 then you are asking for transitions to occur from -9 to +9 from edges (a tight window of 2 ns).
With data and strobe constrained for 2 ns relative to their edges you have ample room of about 8 ns for both setup and hold between strobe transition and data transition.
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Thanks for the suggestion. I tried this, but the requirement seems to be too strict. I also tried +-8 ns without any luck.
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Dear jorkrohn,
- Ensure your strobe is the output of a single register (ie, "dstrobe_reg"). Modify your FSM if needed.
- Create a clock (ie, "dstrobe_reg_clk"), derived from "clk", targetted at the output of "dstrobe_reg".
- Create a clock (ie, "dtrobe_clk"), derived from the former "dstrobe_reg_clk", targetted at the "dstrobe" output pin.
The warning should now be gone and the the "dstrobe_clk" timing should now include all the internal delays.
Constrain the output delays against the "dstrobe_clk".
If your external device samples at the rising edge of dstrobe and it has a 4.8 ns tSU and tH, then all you need is.
set_output_delay -clock dstrobe_clk -max 4.8 [get_ports {dd*}]
set_output_delay -clock dstrobe_clk -min -4.8 [get_ports {dd*}]
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Thanks! Creating the clock constraint in two steps seems to work fine.
Honored Contributor
