Help with constraining a parallel interface

Dear jorkrohn,

- Ensure your strobe is the output of a single register (ie, "dstrobe_reg"). Modify your FSM if needed.

- Create a clock (ie, "dstrobe_reg_clk"), derived from "clk", targetted at the output of "dstrobe_reg".

- Create a clock (ie, "dtrobe_clk"), derived from the former "dstrobe_reg_clk", targetted at the "dstrobe" output pin.

The warning should now be gone and the the "dstrobe_clk" timing should now include all the internal delays.

Constrain the output delays against the "dstrobe_clk".

If your external device samples at the rising edge of dstrobe and it has a 4.8 ns tSU and tH, then all you need is.

set_output_delay -clock dstrobe_clk -max 4.8 [get_ports {dd*}]

set_output_delay -clock dstrobe_clk -min -4.8 [get_ports {dd*}]