Help understanding concepts in VHDL, like to use a FIFO

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I need help understanding how to use a FIFO in VHDL. If I am inside a process and I want to put two bits serially into a FIFO, how is that done?

I need to set the FIFO clock enable high, the write signal high, set the input to the FIFO, wait one clock cycle, repeat it again with the second input bit, and then set the clock enable and write signal low. But that doesn't make conceptual sense with only having access to combinational logic within the process. I'm also assuming using one-shot multivibrators aren't used...

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A process can communicate with any signal declared in the module. It can't communicate with variables declared in other processes.

I don't know what multivibrators are, nor the one-shot version (not at least in the context of fpga), nor their relation to fifo concept

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I need help understanding how to use a FIFO in VHDL. If I am inside a process and I want to put two bits serially into a FIFO, how is that done?

I need to set the FIFO clock enable high, the write signal high, set the input to the FIFO, wait one clock cycle, repeat it again with the second input bit, and then set the clock enable and write signal low. But that doesn't make conceptual sense with only having access to combinational logic within the process. I'm also assuming using one-shot multivibrators aren't used...

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To implement what you've described you need either a state machine or a simple counter. To illustrate the concept, here is a sketch of what the process would look like

process(Clock)
begin
   if rising_edge(Clock) then
      if (Reset = '1') then
         Current_State <= Idle
         Fifo_Write_Enable <= '0';
      else
         case Current_State is
            when Idle =>
               Fifo_Write_Enable <= '0';
               If (I_Got_Some_Input = '1') then
                  Save_This_Data <= Input_Data;
                  Current_State <= Save_First;
               end if;
            when Save_First =>
               Fifo_Write_Enable <= '1';
               Fifo_Write_Data <= Save_This_Data(1);
               Current_State <= Save_Second;
            when Save_Second =>
               Fifo_Write_Enable <= '1';
               Fifo_Write_Data <= Save_This_Data(2);
               Current_State <= Idle;
         end case;
      end if;
   end if;
end process;

The things to take away here are the following:

- It takes multiple clock cycles to store the bits in the fifo because you want to serialize your data

- The state machine is entered on each rising edge of the clock

Kevin Jennings

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To implement what you've described you need either a state machine or a simple counter. To illustrate the concept, here is a sketch of what the process would look like

The things to take away here are the following:

- It takes multiple clock cycles to store the bits in the fifo because you want to serialize your data

- The state machine is entered on each rising edge of the clock

Kevin Jennings

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oooh, I get it now. Thanks!