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Altera_Forum's avatar
Altera_Forum
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13 years ago

Help understanding concepts in VHDL, like to use a FIFO

I need help understanding how to use a FIFO in VHDL. If I am inside a process and I want to put two bits serially into a FIFO, how is that done? I need to set the FIFO clock enable high, th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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To implement what you've described you need either a state machine or a simple counter. To illustrate the concept, here is a sketch of what the process would look like

The things to take away here are the following:

- It takes multiple clock cycles to store the bits in the fifo because you want to serialize your data

- The state machine is entered on each rising edge of the clock

Kevin Jennings

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oooh, I get it now. Thanks!