[Help] QSys generating faulty Verilog code

I currently try to build a QSys Sytem for Cyclone V, where a camera is being connected to hps sdram as avalon mm master and is also connected as avalon mm slave to the lw hps2fpga interface. The lw hps2fpga master also has some other slaves.

Find next an image, where you can see the pinout of the slave and master interfaces of my custom module (CamConnector) in the bottom left corner, the qsys interconnection in the top right corner and the address table in the bottom right corner.

https://thumb.ibb.co/drx2qv/qsys.png (https://ibb.co/drx2qv)

My problem now is, that QSys generates Verilog code, that can't be compiled.

Quartus 2 throws the following error message inside the Merlin router attached to the lw hps2fpga interface.

Error (10232): Verilog HDL error at soc_system_mm_interconnect_2_router.sv(204): index 34 cannot fall outside the declared range [33:0] for vector "address"

Any idea how i can resolve this error?

I don't really like messing with the generated files, so i hope there's just a configuration problem.

Thanks in advance.

Edit: Maybe the generated code at that location is of interest.

    // ( 0x0 .. 0x20 )
    if ( {address,{PAD0{1'b0}}} == 35'h0   ) begin
            src_channel = 8'b00000100;
            src_data = 6;
    end