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Honored Contributor[Help] QSys generating faulty Verilog code
I currently try to build a QSys Sytem for Cyclone V, where a camera is being connected to hps sdram as avalon mm master and is also connected as avalon mm slave to the lw hps2fpga interface. The lw h...
Altera_ForumHonored Contributor
Honored ContributorThanks for the response.
I'm using v16.1. I could resolve this problem though by removing some axi slaves and thus limiting the needed address range. In my opinion the bug is inside the generated files, where a logarithm function is being used to get the number of bits needed for the address width. While the generator might use flooring, the "dynamic" verilog pendant uses ceiling.
