[Help] QSys generating faulty Verilog code

Thanks for the response.

I'm using v16.1.

I could resolve this problem though by removing some axi slaves and thus limiting the needed address range.

In my opinion the bug is inside the generated files, where a logarithm function is being used to get the number of bits needed for the address width.

While the generator might use flooring, the "dynamic" verilog pendant uses ceiling.