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Altera_Forum
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9 years ago

[Help] QSys generating faulty Verilog code

I currently try to build a QSys Sytem for Cyclone V, where a camera is being connected to hps sdram as avalon mm master and is also connected as avalon mm slave to the lw hps2fpga interface. The lw h...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

What version of Quartus are you using? I'm seeing more and more bugs (potentially similar to this) with Q17.0.

Cheers,

Alex