Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Help in VHDL

Hi, i'm working on a algorithm that will do Run-Length data compression. This is what i'm doing: i initialize a matrix and tranform it in a vector and, while doing that, i discover what will be the size of the compressed new vector. Then i try to declare another vector with that size.

Look a small abstract of the algorithm:

PROCESS

TYPE line IS ARRAY (0 TO 3) OF INTEGER;

TYPE matrix IS ARRAY (0 TO 3) OF linha;

variable mat : matrix;

BEGIN

mat := ( (100, 99, 95, 94),

( 98, 96, 93, 0),

( 97, 92, 0, 0),

( 91, 0, 0, 0));

-- THIS IS WHERE THE VECTOR (100, 99,98,97,96,95,94,93,92,91,0,0,0,0,0,0) IS CREATED AND VECTOR_SIZE IS FOUND OUT.

PROCESS

TYPE comp IS ARRAY (0 TO VECTOR_SIZE) OF INTEGER;

variable COMPRESSED_VECTOR : comp;

-- THIS IS WHERE THE VECTOR IS USED TO CREATE THE COMPRESSED VECTOR. THE PROBLEM IS qu(at)rtus WON'T LET ME CREATE AN ARRAY USING A VARIABLE (0 TO VECTOR_SIZE), IT NEED TO BE A CONSTANT.

VECTOR_SIZE IS A SHARED VARIABLE AND I WAS THINKING ABOUT CONVERTING IT TO A CONSTANT, IF THAT'S POSSIBLE

7 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    --- Quote Start ---

    THE PROBLEM IS qu(at)rtus WON'T LET ME CREATE AN ARRAY USING A VARIABLE (0 TO VECTOR_SIZE), IT NEED TO BE A CONSTANT.

    --- Quote End ---

    Yes, according to the VHDL specification. It's not an Altera Quartus problem, particulary.

    As you try to implement variable size arrays, I fear it's only the "tip of the iceberg" or most obvious problem with your coding attempts. There are most likely more constructs, that will never work in synthesizable VHDL. So you may need to spend some time learning the basic concepts of a HDL (hardware description language). It's rather different from a procedural programming language.

    Regarding the said detail problem, you can specify a maximum size for the storage and use it up to a variable limit. That's, by the way, also the common method in C programming.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    So, there is no way to declare the vector with the RIGHTd size. Is that correct?

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Yes, and I also don't see any purpose of doing so. The FPGA register resources can't be aquired from a heap during runtime, you have to assign them statically.

    I don't know, what you exactly want to achieve. But if the problem is basic run-length encoding, you also can perform it without intermediate storage, I think.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    I get the feeling you are trying to write VHDL as a procedural language. The first thing to learn is that HDLs are essentially parrallel languages - you're not listing a load of instructions to be performed one after the other, all assignments happen at the same time.

    You also mention using a shared variable. They are NOT meant to be used for synthesizable code, only for testbenches. Inside an architecture you should use signals to communicate between processes. As shared variable are updated instantly, you cannot garantee what value they will be when read, and the synthesisor will probably convert them to a signal anyway, which may then behave drifferently from how you expect.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    The above posts are all correct - you need to choose a maximum size for your vector. The only thing I'd add is that you could use a generic to more easily change the maximum length. This would mean that if a different design used a different vector length you could use the same piece of code just change the generic map in your component instantiations.

    e.g.

    
    entity your_block is
    generic (max_vector_length : integer := 10)
    port (
                -- the ports in your design
    );
    end your_block;

    then in your designs when you instantiate this block:

    design1 : your_block
    generic map (max_vector_length => 20);
    port map (
                     -- as usual
    );
    design2 : your_block
    generic map (max_vector_length => 37);
    port map (
                     -- as usual
    );

    Essentially because the generic value is known at compile time it is like a constant. It just allows you to more easily change the value and reuse your code more easily.

    Hope this helps.