Help in VHDL

The above posts are all correct - you need to choose a maximum size for your vector. The only thing I'd add is that you could use a generic to more easily change the maximum length. This would mean that if a different design used a different vector length you could use the same piece of code just change the generic map in your component instantiations.

e.g.

entity your_block is
generic (max_vector_length : integer := 10)
port (
            -- the ports in your design
);
end your_block;

then in your designs when you instantiate this block:

design1 : your_block
generic map (max_vector_length => 20);
port map (
                 -- as usual
);
design2 : your_block
generic map (max_vector_length => 37);
port map (
                 -- as usual
);

Essentially because the generic value is known at compile time it is like a constant. It just allows you to more easily change the value and reuse your code more easily.

Hope this helps.