Help in VHDL

I get the feeling you are trying to write VHDL as a procedural language. The first thing to learn is that HDLs are essentially parrallel languages - you're not listing a load of instructions to be performed one after the other, all assignments happen at the same time.

You also mention using a shared variable. They are NOT meant to be used for synthesizable code, only for testbenches. Inside an architecture you should use signals to communicate between processes. As shared variable are updated instantly, you cannot garantee what value they will be when read, and the synthesisor will probably convert them to a signal anyway, which may then behave drifferently from how you expect.