[HELP ] VHDL Parking Lot

Hello guys I have an advance for parking lot, only need the testbench code. If the VHDL code is wrong in some parts, please help me.

Sorry for my english :D

My crystal ball says you have a problem on line 42.

You're welcome.

Here my vhdl code, is something wrong about the design, tell me. So the question is if my vhdl code is good abut the statement of the problem, if I'm missing something, if I'm missing signals

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity parking_lot is
port (detector_1 : in std_logic; -- entrando carro
		detector_2 : in std_logic; -- saliendo carro
		libre : out std_logic;
		lleno : out std_logic
		);
end parking_lot;
architecture behavioral of parking_lot is
begin
	process (detector_1,detector_2)
		begin
			if (detector_1 = '0') then
			libre <= '1';
			elsif (detector_1 ='1') then
			libre <= '0';
			elsif (detector_2 = '0') then
			lleno <= '0';
			elsif (detector_2 ='1') then
			lleno <= '1';
			end if;
		end process;
end behavioral;

i'm trying to design a test bench

Besides once 10 cars have filled the parking lot, it will still report it "free".

It's better to actually write the test bench first, and then see how your code behaves.

I can try being a bit more constructive....

The reason why I say you should begin with the testbench is that it makes you think about what kind of inputs your system will have and how it should react.

Start with something basic. Draw a timing diagram of the signals from the two sensors when a car enters the parking lot. You need to have the whole event, from when the car is completely outside the parking until when it is fully inside. Similarly draw the diagram for when a car exits the parking lot.

Then write two VHDL procedures that generate the sensor signals for both events.

Then you can write your testbench. The parking starts empty, and for example call 9 times the procedure that simulates a car entering the parking lot. During all that time the testbench will also check that the "free" light is always on and will generate an error if it doesn't.

Then call a 10th time the car enter simulating procedure, and check that the "free" light turns off, and the "full" light turns on (allowing a small delay before checking).

Then simulate a car going outside of the parking, and check that the "full" light turns off and the "free" light turns on.

This can be your first test bench to check your code. Ideally you will want to simulate other cases, with several cars going out and in again, just to check that your code behaves correctly in different situations.

Once you have that, and you have a good idea on how the sensors work, you can begin designing your main VHDL code. Note that if you want something that synthesizes, you will probably need a clock, generated in the test bench.