[HELP ] VHDL Parking Lot

Here my vhdl code, is something wrong about the design, tell me. So the question is if my vhdl code is good abut the statement of the problem, if I'm missing something, if I'm missing signals

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity parking_lot is
port (detector_1 : in std_logic; -- entrando carro
		detector_2 : in std_logic; -- saliendo carro
		libre : out std_logic;
		lleno : out std_logic
		);
end parking_lot;
architecture behavioral of parking_lot is
begin
	process (detector_1,detector_2)
		begin
			if (detector_1 = '0') then
			libre <= '1';
			elsif (detector_1 ='1') then
			libre <= '0';
			elsif (detector_2 = '0') then
			lleno <= '0';
			elsif (detector_2 ='1') then
			lleno <= '1';
			end if;
		end process;
end behavioral;