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Altera_Forum
Honored Contributor
Honored ContributorHello_world doesn't work for Arria 10 ubuntu 14.04
1. quartus 17.0, ubuntu 14.04, opencl
2. Arria10 is used. 3. all diagnose pass. command: aoc device/hello_world.cl -o bin/hello_world.aocx --board a10gx Error message in hello_world.log System name: hello_world java: /build/swbuild/SJ/nightly/17.0.2/297/l64/p4/quartus/ccl/ver/ver_jni_stub.cpp:122: jboolean Java_com_altera_version_AlteraProductInfo_initialize(JNIEnv*, jobject): Assertion `success' failed. Aborted (core dumped)23 Replies
Altera_Forum--- Quote Start --- HRZ, I had the same issue. Initially, you said it was my storage being full/unstable. I tried it again on different host machine and storage device and got the same error. Is Quartus 17 tested on CentOS 7 at all? --- Quote End --- You initially replied that your storage was unstable, so I thought the issue has been resolved, but now there are two people reporting the exact same issue on the exact same OS. This could mean the problem might actually be from Altera. I recommend both of you to open a ticket with Altera's support and report the issue. CentOS 7 has been supported since Quartus v16 (or maybe even before that), but they probably do not test every version on every OS. There had been cases before where OpenCL compilation was completely broken in the new version they released. P.S. For the sake of completeness, can you guys temporarily disable SELinux and try again? Of course SELinux must remain enabled for maximum security, but if that is the source of problem, it would be easier to find a solution for it.- Altera_Forum
FYI: I have disabled the SELinux ad tried again. now sestatus command shows SELinux status: disabled.
but I still get same errors. - Altera_Forum--- Quote Start --- it fails to generate kernel_system_avs_kernel_sender_cra_cra_ring.ip --- Quote End --- Got exactly same ip files missing. Running stuff under Windows 10. Have you found solution yet?
- Altera_Forum
I am having the same issues while running Intel FPGA SDK for OpenCL and Quartus 17.0.2 on CentOS Linux release 7.4.1708 and compiling for Arria10.
Intel software generates .aocx files successfully but I am having issues with Quartus projects. I am running the same versions of Quartus and AOC: quartus_map --version: Quartus Prime Analysis & Synthesis Version 17.0.2 Build 297 07/19/2017 SJ Pro Edition aoc --version Intel(R) FPGA SDK for OpenCL(TM), 64-bit Offline Compiler Version 17.0.2 Build 297 These are warnings I get in quartus_sh_comile.log: Warning (16124): Can't analyze file ip/kernel_system/kernel_system_avs_kernel_sender_cra_cra_ring.ip - no such file exists Warning (16124): Can't analyze file ip/kernel_system/kernel_system_avs_reorder_const_cra_cra_ring.ip - no such file exists Warning (16124): Can't analyze file ip/kernel_system/kernel_system_avs_mem_writestream_cra_cra_ring.ip - no such file exists Warning (16124): Can't analyze file ip/kernel_system/kernel_system_boardtest_system.ip - no such file exists Warning (16124): Can't analyze file ip/kernel_system/kernel_system_avs_kernel_receiver_cra_cra_ring.ip - no such file exists Warning (16124): Can't analyze file ip/kernel_system/kernel_system_avs_nop_cra_cra_ring.ip - no such file exists Warning (16124): Can't analyze file ip/kernel_system/kernel_system_avs_mem_readstream_cra_cra_ring.ip - no such file exists Warning (16124): Can't analyze file ip/kernel_system/kernel_system_avs_mem_read_writestream_cra_cra_ring.ip - no such file exists These are errors I get in quartus when compiling project: Error: Error opening /home/plokhovska/helloworld/hello_world/bin/hello_world/ip/kernel_system/kernel_system_avs_kernel_sender_cra_cra_ring.ip. Error: Error opening /home/plokhovska/helloworld/hello_world/bin/hello_world/ip/kernel_system/kernel_system_avs_reorder_const_cra_cra_ring.ip. Error: Error opening /home/plokhovska/helloworld/hello_world/bin/hello_world/ip/kernel_system/kernel_system_avs_mem_writestream_cra_cra_ring.ip. Error: Error opening /home/plokhovska/helloworld/hello_world/bin/hello_world/ip/kernel_system/kernel_system_boardtest_system.ip. Error: Error opening /home/plokhovska/helloworld/hello_world/bin/hello_world/ip/kernel_system/kernel_system_avs_kernel_receiver_cra_cra_ring.ip. Error: Error opening /home/plokhovska/helloworld/hello_world/bin/hello_world/ip/kernel_system/kernel_system_avs_nop_cra_cra_ring.ip. Error: Error opening /home/plokhovska/helloworld/hello_world/bin/hello_world/ip/kernel_system/kernel_system_avs_mem_readstream_cra_cra_ring.ip. Error: Error opening /home/plokhovska/helloworld/hello_world/bin/hello_world/ip/kernel_system/kernel_system_avs_mem_read_writestream_cra_cra_rin g.ip. - Altera_Forum
@Zhanneta
Also using 17.0.2 same warnings/errors in quartus_sh_comile.log/quartus project compilation log The only difference is that I'm using Windows 10, as I posted in my first post. - Altera_Forum
I just tested v17.0.2 on my own environment. The standard PR (Partial Reconfiguration) flow works fine, but the flat flow is indeed broken. I get the same error as everyone else. Still, the default flow should be the PR flow and I am wondering why you guys are being defaulted to the flat flow. I will open a support request with Altera.
- Altera_Forum--- Quote Start --- I just tested v17.0.2 on my own environment. The standard PR (Partial Reconfiguration) flow works fine, but the flat flow is indeed broken. I get the same error as everyone else. Still, the default flow should be the PR flow and I am wondering why you guys are being defaulted to the flat flow. I will open a support request with Altera. --- Quote End --- HRZ, thanks for an answer and the tip. Still wondering how to force/set explicitly that PR flow? Currently trying --bsp_flow base command and wating for results. Am I on the right track? Also, is it possible that flat flow is defaulted because I don't have an actual board plugged in?
- Altera_Forum
So, it works with --bsp_flow base
At least I was able to do Analysis@Synthesis and Place and Route in Quartus with no problems. Don't now yet if it really works as intended as a sheme. - Altera_Forum
To be honest I am not sure. I only know how to force the flat flow, I have no idea how to force the PR flow. The PR flow has always been the default flow and on my environment, the compiler still seems to default to that flow even with 17.0.2. I checked altera's documents again for v17, there is no mention of the flat flow. Even though this flow has existed for a long time, it was never documented, but they seem to have changed something in v17.0.2. Assuming that aoc accepts the "--bsp_flow" switch, I think you should probably use "--bsp_flow top" rather than "base" for the standard PR flow, but I could be wrong.
Regarding the board being connected or not, compilation does not require the board to be present and whether the board is present or not should not make any difference in this case. - Altera_Forum--- Quote Start --- To be honest I am not sure. I only know how to force the flat flow, I have no idea how to force the PR flow. The PR flow has always been the default flow and on my environment, the compiler still seems to default to that flow even with 17.0.2. I checked altera's documents again for v17, there is no mention of the flat flow. Even though this flow has existed for a long time, it was never documented, but they seem to have changed something in v17.0.2. Assuming that aoc accepts the "--bsp_flow" switch, I think you should probably use "--bsp_flow top" rather than "base" for the standard PR flow, but I could be wrong. Regarding the board being connected or not, compilation does not require the board to be present and whether the board is present or not should not make any difference in this case. --- Quote End --- I tried compiling one of Intel design examples with "--bsp_flow top" and I am still receiving the same errors.
