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AHoll13's avatar
AHoll13
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5 years ago

Hello. I'm new to FPGAs/CPLDs, and am doing a project with the MAX V 5M160ZE64A5N CPLD and am getting timing failures with a 100MHz clock.

The 100MHz clock is clocking I/O and generating time delays in the logic circuit. I have used the Timing Analyzer and SDC file to constrain the clock, as well as the I/O, however I am getting errors ...
AHoll13's avatar
AHoll13
Icon for New Contributor rankNew Contributor
5 years ago

I removed the clocks from all inputs and outputs, as they were not required and actually causing application issues. And I introduced a second timer on each of the 6 sub-circuits, as using one single timer was also causing application issues. I am using the data signal as the clrn control for the flip-flops as again, for my application, I would like to clear them when this signal is low - is this how this function is intended to be used?

I've experimented with disconnecting the clock signal from some of the flip-flops in order to play with the fanout. Although the number of flip-flops connected to the clock signal did change the slack, there was no correlation between the fanout number and the amount of slack - ie. reducing the fanout didn't necessarily reduce the negative slack and increasing fanout didn't necessarily increase negative slack.

Many thanks