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AHoll13's avatar
AHoll13
Icon for New Contributor rankNew Contributor
5 years ago

Hello. I'm new to FPGAs/CPLDs, and am doing a project with the MAX V 5M160ZE64A5N CPLD and am getting timing failures with a 100MHz clock.

The 100MHz clock is clocking I/O and generating time delays in the logic circuit. I have used the Timing Analyzer and SDC file to constrain the clock, as well as the I/O, however I am getting errors ...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
5 years ago

Well, now instead of large clock skew, you have large data path delays. What did you change in your design? Why are you using the data signal as the clrn control on the registers? The large fanout there could be the problem now.

#iwork4intel