Hello, I would like to know how do I code fixed point arithmetics (add/sub/divide/multiply/abs/round) for cyclone V FPGA device. I am coding VHDL on Quartus prime standard edition version 18.1

Hello DKras4

IP blocks for calculations can be found as indicated above.

Included one of my test projects I am working on, it does calculations in floating point and fixed point with ip blocks (and a natural logarithm ln()). You might get some inspiration out of it. All is targeted Cyclone V DE10_STANDARD.

If you want to do only simple fixed point calculations, you can code it directly in VHDL, no need for IP blocks.

Below a timer component that effectively counts clock pulses to wait for a certain period of time.

The objective of the block is to extend the signal "Ein" for a certain period of time.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;entity ent_sa_timer is
generic( clk_f  : in real:=50.0E6;
			t      : in time:=1sec);
	port( clk    : in std_logic; 
			reset_p: in std_logic:='0';
			ein    : in std_logic;
			aus    : out std_logic);
end entity;
 
 
architecture arch_sa_timer of ent_sa_timer is
 
signal ctr       : integer:=0;
signal T_Clock   : time:=1.0/clk_f*1sec;
signal ein_local : std_logic;
 
begin
  process (clk, reset_p)
  begin
		if rising_edge(clk) then
			if ein_local='1' then
				ctr<=ctr;
			elsif ctr>0 then
				ctr<=ctr-1;
			end if;
			ein_local<=ein;
		end if;		 
  end process;
  aus<='1' when ctr>0 else '0';  
end architecture;

The line ctr<=ctr-1 decreases the value of ctr with 1 each time there is a rising_edge of clk.

You can do all kinds of mathematical functions with it mod * + / etc. and you can combine other variables as well.

No need to parametrize Ip blocks for these simple functions.

Best Regards,

Johi.