Hello, I am writing a verilog code from my DE10-Lite Board to scroll the a word or number but keep having errors. Would you be able to help?

Error (10170): Verilog HDL syntax error at Shift code, modified but not working yet.v(21) near text: "wire"; expecting a direction. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

Error (10170): Verilog HDL syntax error at Shift code, modified but not working yet.v(74) near text: "assign"; expecting "endcase". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

Error (10170): Verilog HDL syntax error at Shift code, modified but not working yet.v(74) near text: '. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

Error (10170): Verilog HDL syntax error at Shift code, modified but not working yet.v(148) near text: ")"; mismatched closing parenthesis . Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

Error (10170): Verilog HDL syntax error at Shift code, modified but not working yet.v(162) near text: "}"; expecting ":", or ",". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

Error (10170): Verilog HDL syntax error at Shift code, modified but not working yet.v(162) near text: "{"; expecting "}". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

Error (10170): Verilog HDL syntax error at Shift code, modified but not working yet.v(181) near text: "assign"; expecting an operand. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

Error (10170): Verilog HDL syntax error at Shift code, modified but not working yet.v(185) near text: "endmodule"; expecting "endcase". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

Info (12021): Found 0 design units, including 0 entities, in source file shift code, modified but not working yet.v

Info (144001): Generated suppressed messages file C:/Users/ceedwards/Downloads/Quartus files downloaded/DE10_LITE_Default ADD CODE to CODE STRUCTURE_project/PROJECT C HEX Modified_restored/top.map.smsg