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Altera_Forum's avatar
Altera_Forum
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13 years ago

Half a clock tree?

Hello All,

I'm having troubles with getting a regular IO pin to be routed to a clock tree.

Quartus II 12.0 has managed to put approximately half the flip-flops on a global clock like I specified with: 

set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to FPGA_IO
(The Assignment Editor confirms that it is set)

However, looking at the Technology Map Viewer I see the rest of the registers are wired directly to the FPGA_IO[7] pin!

I added the assignment because even with 'Auto Global Clock' On it put the 1200 flip-flops on internal routing with a lot of hold-time buffering to correct the timing.

Is there a report generated that states which attributes/directives have been recognized, accepted and not ignored!?

I'm wondering what I should do now. Turn off automatic global signal insertion and explicitly instantiate the CLKCTRL everywhere?

The only reason I'm worrying about this is that this part of the design is not working reliably - some builds work, some don't...

Regards,

++Simon

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    The problem arises from the fact that regular pins can't directly drive the global clock trees, it must be feeded through a logic element first.

    Quartus was never very good at doing it automatically, but it's easy to do it by hand.

    Just feed the signal from the pin to an LCELL primitive and then use the output to clock the design.

    LCELL lc (.in(FPGA_IO[7]), .out(clk));

    Quartus should have no problem using a global clock tree for "clk" then, even without the global assignment.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Many thanks for the Guru tip! I've been at a loss to know what to try further.

    I would have normally put the clock on a dedicated clock input pin except that this is on a pre-designed connector to JTAG (a separate JTAG to the FPGA configuration one).

    Best Regards,

    ++Simon
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Just following up. Unfortunately the LCELL did not fix the problem.

    But it seems that the flip-flops not being put on the global clock line were hidden in a partition with the automatically set 'post-fit' type. I moved them to 'Source File' (always gets re-synthesized) and now everything is happily on the global buffers.

    Sometimes I wonder if the 'make' like features of SW might actually cost more time than they save!

    I did find, buried in the fitter info messages, that it mentioned it was not connecting these flip-flops to the global clock. I would have been nice to give this as a critical warning especially as I had purposely assigned them...

    ++Simon