Half a clock tree?

The problem arises from the fact that regular pins can't directly drive the global clock trees, it must be feeded through a logic element first.

Quartus was never very good at doing it automatically, but it's easy to do it by hand.

Just feed the signal from the pin to an LCELL primitive and then use the output to clock the design.

LCELL lc (.in(FPGA_IO[7]), .out(clk));

Quartus should have no problem using a global clock tree for "clk" then, even without the global assignment.