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Altera_Forum's avatar
Altera_Forum
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16 years ago

GLOBAL_SIGNAL assignment for internal net.

Hi All,

I'm trying to assign one of internal signals in my design to a global clock line.

Attached is a very simple Quartus design that would allow anyone interested to reproduce my original issue. While this is not the design I'm working on it will help to show what I'm trying to achieve.

In TopLevel.vhd I instantiate 3 components. One of them is a simple AND gate that takes two signals from fpga pads and ands them. Output of this operation is fed into another module and will act as my clock. Also in the top level vhdl file I declared 'MyGatedClock' signal. Now I need to apply GLOBAL_SIGNAL constraint to MyGatedClock to promote it to a global clock signal in Quartus. I need to do it manually as I have more signals that are global in my design and there are simply not enough global lines within fpga so which one is global is my conscious decision.

The problem is that when I synthesize my example and go to assign logic options in the Assignment Editor I can't find MyGatedClock signal in the Node Finder.

I set filter to "Design Entry (all names) and use * as name and scope is set to top level but when I hit 'List' I'm presented with all ports and signals from my code bar 'MyGatedClock'.

So the question is: How do I get to my signal so I can enable 'global_signal option for it.

Perhaps I missed something simple here?

I'm on Quartus 9.0.

Best Regards,

Rafal

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Hi

    one option is inserting the Global buffer primitive on the mygatedclock signal after the combo and logic. this will direct the sysnthesis tool to route the signal as global signal.

    regards,

    Shubha
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Hi Shubha,

    I considered this option however it's not so simple in my case. The file that binds all components together is autogenerated and will change every time I regenerate it. I know signal name but I can't really inject anything in that particular file.

    Originally, I found this problem when I tried to use global_signal constraint in tcl script and run quartus_sh with my scripts. It didn't work for me so I tried to do same thing in Quartus GUI to check if I missed something in that constraint syntax.

    This is where I got puzzled by a missing signal in the Node Finder.

    Best Regards,

    Rafal
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    --- Quote Start ---

    Hi Shubha,

    I considered this option however it's not so simple in my case. The file that binds all components together is autogenerated and will change every time I regenerate it. I know signal name but I can't really inject anything in that particular file.

    Originally, I found this problem when I tried to use global_signal constraint in tcl script and run quartus_sh with my scripts. It didn't work for me so I tried to do same thing in Quartus GUI to check if I missed something in that constraint syntax.

    This is where I got puzzled by a missing signal in the Node Finder.

    Best Regards,

    Rafal

    --- Quote End ---

    Hi Rafall,

    which signal do you want as global signal ?

    When you look into the Fitter results in the compilation message window under :

    Fitter -> Resource Section -> Global & other Fast Signals

    that the CLK_GATE_OUT is connected to a global net.

    Kind regards

    GPK