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Altera_Forum
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16 years ago

GLOBAL_SIGNAL assignment for internal net.

Hi All, I'm trying to assign one of internal signals in my design to a global clock line. Attached is a very simple Quartus design that would allow anyone interested to reproduce my origi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Hi

one option is inserting the Global buffer primitive on the mygatedclock signal after the combo and logic. this will direct the sysnthesis tool to route the signal as global signal.

regards,

Shubha