getting error in digiclock project..help me..

hii.

i am doing project on altera de1 board on digi clock.

when i compile the program i am getting error in the following line (c1: sec_clk port map(clkm,rstsec,sflag);

it shows node c1 instantiates undefined entity'sec_clk'

pls help me..

thanks.

code is given below:

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity DigiClock is

port(

clkm: in std_logic;

rst,setm,seth: in std_logic;

z: in std_logic;

op: out std_logic;

op0,op1,op2,op3: out std_logic_vector(6 downto 0)

);

end DigiClock;

architecture clock of DigiClock is

component sec_clk

Port (

clks : in std_logic;

rsts : in std_logic;

ops : out std_logic

);

end component;

component min_clk

Port (

clkmi : in std_logic;

rst : in std_logic;

opm : out std_logic

);

end component;

component manu_clk

Port (

set : in std_logic;

clk : in std_logic;

opu : out std_logic

);

end component;

component seg7

port(m: in integer range 0 to 10;

num: out std_logic_vector(6 downto 0));

end component;

signal mflag: std_logic;

signal sflag: std_logic;

signal a: integer range 0 to 10;

signal b: integer range 0 to 6;

signal c: integer range 0 to 10;

signal d: integer range 0 to 3;

signal x: std_logic;

signal hrt: std_logic;

signal t: std_logic;

signal u: std_logic;

signal v: std_logic;

signal rstsec: std_logic;

signal mi: std_logic;

signal hr: std_logic;

begin

c1: sec_clk port map(clkm,rstsec,sflag);

c2: min_clk port map(sflag,rst,mflag);

c3: manu_clk port map(setm,clkm,mi);

c4: manu_clk port map(seth,clkm,hr);

op<=sflag;

delayt: process(clkm,z)

begin

if rising_edge(clkm) then

t<= z;

end if;

end process delayt;

clockmin: process(x,rst,u)

variable m0: integer range 0 to 10:=0;

variable m1: integer range 0 to 6:=0;

begin

a<=m0;

b<=m1;

hrt<= '1' and u;

if rst='0' then

m0:=0;

m1:=0;

elsif falling_edge(x) then

if m0/=9 then

m0:= m0+1;

u<='0';

elsif m0=9 and m1/=5 then

m0:=0;

m1:= m1+1;

u<='0';

elsif m0=9 and m1=5 then

m0:=0;

m1:=0;

u<='1';

end if;

end if;

end process clockmin;

selecter: process(t,hr,mi,mflag,hrt)

begin

if t = '0' then

x<=mi;

v<=hr;

rstsec<='0';

else

x<=mflag;

v<=hrt;

rstsec<='1';

end if;

end process selecter;

clockhr: process(v,rst)

variable m2: integer range 0 to 10:=2;

variable m3: integer range 0 to 3:=1;

begin

c<=m2;

d<=m3;

if rst = '0' then

m2:=2;

m3:=1;

elsif rising_edge(v) then

if m2/=9 and m3=0 then

m2:=m2+1;

elsif m2=9 and m3=0 then

m2:=0;

m3:=m3+1;

elsif m2/=2 and m3=1 then

m2:=m2+1;

elsif m2=2 and m3=1 then

m2:=1;

m3:=0;

end if;

end if;

end process clockhr;

z0: seg7 port map(a,op0);

z1: seg7 port map(b,op1);

z2: seg7 port map(c,op2);

z3: seg7 port map(d,op3);

end clock;