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Altera_Forum
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13 years ago

getting error in digiclock project..help me..

hii. i am doing project on altera de1 board on digi clock. when i compile the program i am getting error in the following line (c1: sec_clk port map(clkm,rstsec,sflag); it shows node c1 in...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Hi,

sounds like neither the project directory itself nor the "project files" definition include the instantiated (Sub)modules instantiated by Component xyz. Thus the compiler cannot "open" these modules for compilation...