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Altera_Forum's avatar
Altera_Forum
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15 years ago

generics in top level vhdl

Hello!

I want to create a SOPC component with parameters, so my top level vhdl file must contain the corresponding generics.

I have a block diagram with several logic elements and vhdl components. Two of these vhdl components have generics. When I'm creating a vhdl design file of this block diagram (Create HDL Design File for Current File), the resulting vhdl file doesn't contain any generics from the included vhdl components in the block diagram.

Is it possible to crate such a vhdl file automatically or do I have to edit it manually?

Thanks!

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    i'm not quite sure of what you're trying to do.

    i have a Verilog file with 2 parameters (generics) which i've created a .bsf for. i place the .bsf into my .bdf, and assign values to the 2 parameters. i create a VHDL file for the .bdf and there are generic maps for my parameters.

    do you see the same? maybe you want to pipe those generics up to the generated VHDL file? not sure this is possible
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Yes, this is it. I want to pipe these generics to my generated vhdl file. Any ideas, if this is feasible?

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    might be easier to write VHDL at some point. have you looked at direct instantiation and generate statements? connecting blocks can be done pretty efficiently.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Usually I would do this manually, i.e. write the top-level VHDL myself. But I guess you can create it automatically (or semi-automatically) too.

    When you generate a VHDL file from your block diagram (using Create HDL Design File for Current File), you should see all your components plus the connections and logic between them inside the VHDL. If you look closely, your components in this VHDL should include those 2 VHDL entities (with generics) that you mentioned earlier. These generics should also appear as the generics inside both of the components in your generated VHDL like this (this is just an example for illustration): 

    
COMPONENT entityA
GENERIC (a1 : INTEGER;
            a2: BOOLEAN;
            a3 : STD_LOGIC_VECTOR(7 DOWNTO 0);
            a4 : INTEGER
            );
    PORT(...);
END COMPONENT;
COMPONENT entityB
GENERIC (b1 : INTEGER
            );
    PORT(...);
END COMPONENT;
    Now, here we need to do a bit of extra work to let these generics propagate to the top-level entity of this VHDL file. 

    
LIBRARY ieee;
USE ieee.std_logic_1164.all; 
LIBRARY work;
ENTITY top_level IS 
    generic(a1:integer;
                 a2:boolean;
                 a3:std_logic_vector(7 downto 0);
                 a4:integer;
                 b1:integer);
    PORT
    (
    );
END top_level;
ARCHITECTURE bdf_type OF top_level IS 
COMPONENT entityA
...
END COMPONENT;
/* similar for entityB */
...
BEGIN 
...
b2v_inst : entityA
GENERIC MAP(a1 => a1,
            a2 => a2,
            a3 => a3,
            a4 => a4
            )
PORT MAP(...);
b2v_inst1 : entityB
GENERIC MAP(b1 => b1
            )
PORT MAP(...);
END bdf_type;
    That's it. Just add a generics clause to the top-level entity, and change (or remap) the generics of each of the VHDL components to the top-level entity instead of its default values.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Thanks for your suggestion. I changed my generated vhdl file similar to your modification (but your modifiaction is smarter than mine :)). I thought, perhaps I've just overseen a possibility to generate it full automatically. Editing it manually doesn't matter, since it works fine!