Altera_Forum
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13 years agoGeneric component inside generic component
Hello.I am designing a vhdl code that has a generic size setting a bunch of operations.I cannot synthetize it with quartus (Error (10346): VHDL error at mac.vhd(7): formal port or parameter "width" must have actual or default value), but I am able to compile with modelsim.My question is, can I put a generic component inside another? If dont, how should I proceed?
entity mac is generic ( width : integer); -- QUARTUS POINTS HERE port ( clk : instd_logic; rst : instd_logic; a_i : instd_logic_vector(width-1downto0); b_i : instd_logic_vector(width-1downto0); acc : instd_logic_vector(2*width-1downto0); out_o : outstd_logic_vector(2*width-1downto0) ); end mac; architecture bhv of mac is component mul generic ( W_g : integer); port ( clk : instd_logic; rst : instd_logic; a_i : instd_logic_vector(W_g-1downto0); b_i : instd_logic_vector(W_g-1downto0); outm_o : outstd_logic_vector(2*W_g-1downto0) ); endcomponent; component soma generic ( W_gs : integer); port ( clk : instd_logic; rst : instd_logic; outm_o : instd_logic_vector(2*W_gs-1downto0); acc : instd_logic_vector(2*W_gs-1downto0); outs_o : outstd_logic_vector(2*W_gs-1downto0) ); endcomponent;