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- Altera_Forum
Honored Contributor
Examine the technology map to see the real FPGA implementation.
Hi,
I have make simple program as below where a is "input" port,b is "output" port and x is "wire". buf b1(x,a); buf b2(b,x); Here if i take b as "inout" port it is generating one extra buffer in RTL view.What is the reason?Examine the technology map to see the real FPGA implementation.