Generating ALTPLL with the Command Line

I found a solution:

Thanks for sharing your solution.

I found an even better solution: Quartus models the PLL and RAM megafunctions (IP blocks) as parametrised HDL modules, so you can instantiate it directly. I'm auto-generating (for example) the Verilog code:

// For the MAX 10 (and Cyclone IV and below):
altpll# (
 .operation_mode("NO_COMPENSATION"),
 .inclk0_input_frequency(20000), // 50 MHz
 .clk0_multiply_by(1),
 .clk0_divide_by  (5),
 .clk1_multiply_by( 1),
 .clk1_divide_by  (10),
 .clk2_multiply_by( 1),
 .clk2_divide_by  (20),
 .clk3_multiply_by( 1),
 .clk3_divide_by  (40),
 .clk4_multiply_by( 1),
 .clk4_divide_by  (80),
 .width_clock(5)
)PLL(
 .inclk ({1'b0, Clk}),
 .clk   (Clk_Out),
 .locked(Locked)
);
// For the Cyclone V (and any other higher-end modern FPGA):
altera_pll# (
 .fractional_vco_multiplier("false"),
 .reference_clock_frequency("50 MHz"),
 .operation_mode("direct"),
 .number_of_clocks(5),
 .output_clock_frequency0("10 MHz"),
 .output_clock_frequency1("5 MHz"),
 .output_clock_frequency2("2.5 MHz"),
 .output_clock_frequency3("1.25 MHz"),
 .output_clock_frequency4("0.625 MHz"),
 .pll_type("General"),
 .pll_subtype("General")
)PLL(
 .rst   (Reset),
 .outclk(Clk_Out),
 .locked(Locked),
 .refclk(Clk)
);

this solution looks longer in term of code size.

It's because it's a more elaborate example. The equivalent of the batch file I posted earlier is:

altpll# (
 .operation_mode("NO_COMPENSATION"),
 .inclk0_input_frequency(20000), // 50 MHz
 .clk0_multiply_by(1),
 .clk0_divide_by  (5),
 .width_clock(5)
)PLL(
 .inclk ({1'b0, Clk}),
 .clk   (Clk_Out),
 .locked(Locked)
);

The way I usually do it is generating the core from Qsys GUI. Then go to its log window, and copy the entire command +parameters.

I'll definitely keep this in mind for automating the more complex IP blocks - thank you :-)