Generating ALTPLL with the Command Line

The way I usually do it is generating the core from Qsys GUI. Then go to its log window, and copy the entire command +parameters.

High-level command in Quartus 15.x is qsys-generate.

The command looks something like this (just copying from my script):

$ALTERA_PATH/sopc_builder/bin/qsys-generate

$qsys_name

--synthesis=VERILOG

--output-directory="$qsys_dir"

--family="$fpga_family"

--part="$fpga_part" 2>&1 | tee -a $LOGFILE