generating a .vo file without the fitter

--- Quote Start ---

The quartus handbook shows 2 ways to generate a vo file without running the fitter:

quartus_map <project name> -c <revision name> r

quartus_sta <project name> -c <revision name> --post_map r

or

quartus_tan <project name> -c <revision name> --post_map --

zero_ic_delays r

quartus_eda <project name> -c <revision name> --simulation

--tool= <3rd party eda tool> --format=<HDL language> r

When I try the first way (quartus_sta), I get this error:

altera.eda.rpt:Error: Run the Fitter (quartus_fit), followed by the Timing Analyzer (quartus_tan or quartus_sta), before running the EDA Netlist Writer (quartus_eda)

When I try the second way (quartus_tan), I get this error:

Error: Device family Stratix IV is not supported by the Classic Timing Analyzer

Has anyone successfully created a vo file without running the fitter on a Stratix 4 device ?

Thanks

--- Quote End ---

Hi,

the vo-file based on the netlist after Place&Route. Not only the netlist is generated also the delays of the design is extracted ( the vo-file reads the sdo file ). Therefore you have to run the fitter before you can generate the vo-file.

Your second problem is timing analyzer related. Quartus offers two timing analyzer. The old "Classic" (Quartus_tan) and the newer "TimeQuest" (Quartus_sta)Timing analyzer. StratixIV is not support by the Classic timing analyzer. I must use Timequest.

Kind regards

GPK

While that (fitter required) does seem to be the case, the quartus handbook explicitly states (from just before my post):

"If you want to generate a post-synthesis simulation netlist with just the cell delays,

you can generate an .sdo file without running the fitter. In this case, the .sdo file

includes all timing values for only the device cells. Interconnect delays are not

included because fitting (placement and routing) has not been performed. To generate

the post-synthesis netlist and the .sdo file, type the following commands at a

command prompt:"

It wouldn't be the first time that some documentation was wrong...........

--- Quote Start ---

While that (fitter required) does seem to be the case, the quartus handbook explicitly states (from just before my post):

"If you want to generate a post-synthesis simulation netlist with just the cell delays,

you can generate an .sdo file without running the fitter. In this case, the .sdo file

includes all timing values for only the device cells. Interconnect delays are not

included because fitting (placement and routing) has not been performed. To generate

the post-synthesis netlist and the .sdo file, type the following commands at a

command prompt:"

It wouldn't be the first time that some documentation was wrong...........

--- Quote End ---

Hi,

I could achieve what you want, but only by modifying project settings. When you open :

Assignments -> EDA tool settings -> Simulation -> More EDA Netlist writer Settings

you have to set "Generate Netlist for functional simulation only"

Kind regards

GPK