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Altera_Forum's avatar
Altera_Forum
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17 years ago

Generating a clock signal in the VWF

Hi all

I'm a recent noob to VHDL and have made pretty good progress to date using a set of books and searching through fora archives. However, I have a problem now that I can't find any information on. I'm trying to define one of my input in the VWF file as a clock. I right click on the input and select value and then clock. I would like to define a 10Mhz clock with a half-cycle offset. So I enter 10us for the period and 5us for the offset. I want the clock to have a time range of 5s. Everytime I try to enter this information I get errors such as "Specifiy a legal period", or "Specify a legal offset", or "Specify a legal end time". Whatever end time I select I cannot get it accepted. The is clearly some relationship between these various input parameters (and maybe others) that I do not understand.

Any thoughts? It's really making me feel a bit dumb, as I've managed to build circuits that a quite complex and yet I can't even define a clock properly :-(

Many thanks in advance for your guidance.

Kindest regards

Kurt

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    When you got "Specify a legal end time", you probably had "End time" in the "Clock" dialog box set to a larger value than you had for the overall file at "Edit --> End Time".

    Since 10 MHz is not a 10 us period, I assume you had a typo in your post.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    If you're learning VHDL, I would recommend taking a look at learning VHDl testbenches. With a vector waveform file, you have very limited testing capabilities, in that you run data through it and see what comes out the other side. For some applications this may be all right(like video editing, where you just dump a video feed into it), but for things more complex, a testbench lets you write higher-level functions that actually make decisions based on what the DUT(device under test, i.e. your source code) does.

    (And that doesn't mean I don't use simple waveform entry now and then, since it's so quick if there's only condition I want to test on a low-level function.)
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Many thanks Brad and Rysc

    I thought I'd already set the end time correctly, but obviously not. After following your guidance Brad the simulation runs just how I need it to... great sigh of relief my end.

    Thanks for the recommendation Rysc. I expect to be doing much more complex simulations in the future and so will certainly checkout the testbench approach.

    Thanks again to both of you.

    Kindest regards, Kurt
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    --- Quote Start ---

    Many thanks Brad and Rysc

    I thought I'd already set the end time correctly, but obviously not. After following your guidance Brad the simulation runs just how I need it to... great sigh of relief my end.

    Thanks for the recommendation Rysc. I expect to be doing much more complex simulations in the future and so will certainly checkout the testbench approach.

    Thanks again to both of you.

    Kindest regards, Kurt

    --- Quote End ---

    Hi Kurt,

    for starting with advanced simulation tools you can download a Modelsim Altera Web Edition from the Altera Homepage.

    http://www.altera.com/products/software/quartus-ii/modelsim/qts-modelsim-index.html

    It supports only small FPGA's, but it is for free.