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Altera_Forum's avatar
Altera_Forum
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17 years ago

Generating a clock signal in the VWF

Hi all I'm a recent noob to VHDL and have made pretty good progress to date using a set of books and searching through fora archives. However, I have a problem now that I can't find any infor...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

When you got "Specify a legal end time", you probably had "End time" in the "Clock" dialog box set to a larger value than you had for the overall file at "Edit --> End Time".

Since 10 MHz is not a 10 us period, I assume you had a typo in your post.