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Altera_Forum
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17 years ago

Generating a clock signal in the VWF

Hi all I'm a recent noob to VHDL and have made pretty good progress to date using a set of books and searching through fora archives. However, I have a problem now that I can't find any infor...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Many thanks Brad and Rysc

I thought I'd already set the end time correctly, but obviously not. After following your guidance Brad the simulation runs just how I need it to... great sigh of relief my end.

Thanks for the recommendation Rysc. I expect to be doing much more complex simulations in the future and so will certainly checkout the testbench approach.

Thanks again to both of you.

Kindest regards, Kurt