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Albert_Waissman's avatar
Albert_Waissman
Icon for New Contributor rankNew Contributor
2 years ago

Generated simulation model for intel_agilex_hps do not provide implementation for f2h_ace interface

Hello, I found that generated simulation mode by design platform for HPS do not provide implementation for this interface. This interface get passed all the way to: my_hps.intel_agilex_hps_0.intel...
Simulation
tehjingy_Altera's avatar
tehjingy_Altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

Hi


Do you have any follow up question on HPS Simulation?


Regards

Jingyang, Teh


  • awaissman's avatar
    awaissman
    Icon for New Contributor rankNew Contributor
    1 year ago

    Hi,

    Unfortunately i still not able to see simulation.

    When i try run simulation from:

    agilex5_hps_f2h_simulation/agilex5_hps_f2h_simulation/sim/mentor

    I am getting following error:

    # ** FATAL: Questa VIP version mismatch detected.
    # ** There is a mismatch between the SystemVerilog (version = 20220701) and the BFM (version = 20240212).
    # ** Please check your compilation and simulation commands to ensure a consistent QVIP version is in use.

    I see this type of error first time.

    Questa version 2023.4_3

    Quartus version 24.2

    Thanks,