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Altera_Forum's avatar
Altera_Forum
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11 years ago

generate *.pin file

Hello everyone, Do you know how to generate *.pin file for my FPGA from Quartus II? This *.pin file will contain all pin assignments and also the voltage of each bank.

The format of this file is like the below: 

--------------------------------------------------------------------------------- -- Pin directions (input, output or bidir) are based on device operating in user mode.
 ---------------------------------------------------------------------------------
Quartus II 64-Bit Version 14.1.0 Build 186 12/03/2014 SJ Full Version
CHIP  "dpinput"  ASSIGNED TO AN: 5AGXBA3D4F31C4
Device Migration List: "5AGXBA5D4F31C4, 5AGXBA7D4F31C4"
Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
-------------------------------------------------------------------------------------------------------------
NC                           : A2        :        :                   :         :           :                
NC                           : A3        :        :                   :         :           :                
dp2_select_led               : A4        : output : 3.3-V LVTTL       :         : 7A        : Y              
dp2_sync_led                 : A5        : output : 3.3-V LVTTL       :         : 7A        : Y              
RESERVED_INPUT_WITH_WEAK_PULLUP : A6        :        :                   :         : 7A        :                
NC                           : A7        :        :                   :         :           :                
NC                           : A8        :        :                   :         :           :                
VCCIO7B                      : A9        : power  :                   : 1.5V    : 7B        :                
dp2_aux_tx                   : A10       : output : 1.5 V             :         : 7B        : Y              
dp2_aux_rx                   : A11       : input  : 1.5 V             :         : 7B        : Y              
VCCIO7C                      : A12       : power  :                   : 2.5V    : 7C        :                
RESERVED_INPUT_WITH_WEAK_PULLUP : A13       :        :                   :         : 7C        :                
dp2_hpd_snk                  : A14       : output : 2.5 V             :         : 7C        : Y              
RESERVED_INPUT_WITH_WEAK_PULLUP : A15       :        :                   :         : 7C        :                
RESERVED_INPUT_WITH_WEAK_PULLUP : A16       :        :                   :         : 7D        :                
RESERVED_INPUT_WITH_WEAK_PULLUP : A17       :        :                   :         : 7D        :                
VCCIO7D                      : A18       : power  :                   : 2.5V    : 7D        :

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    It should be one of the outputfiles after generating the design.

    Should be generated by the Fitter...
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    --- Quote Start ---

    Do you know how to generate *.pin file for my FPGA from Quartus II? This *.pin file will contain all pin assignments and also the voltage of each bank.

    --- Quote End ---

    I believe what you are asking is how to automate the pin assignments, so that you do not have to repeat it.

    The solution is to use a Tcl script with the pin assignments. Take the design that you used to generate the *.pin file above (i.e., that file was generated when you synthesized that design). In the Quartus GUI select "Project->Generate Tcl file for Project" and look at the generated file. Inside that file you will see the Tcl statements that implement the pin assignments, and a lot more Tcl functions that setup the design.

    Now, go and take a look at a few of the example designs I have posted, eg.,

    Post#2

    http://www.alteraforum.com/forum/showthread.php?t=45927

    Post#20

    http://www.alteraforum.com/forum/showthread.php?t=45748&page=2

    Perform the steps in the readme.txt file, then use "Project->Generate Tcl file for Project" to generate a Tcl file, then go and take a look at constraints.tcl and synth.tcl. constraints.tcl contains the pin assignments and is reusable for any design that uses this board. synth.tcl is specific to a project and sets up the Quartus GUI.

    Cheers,

    Dave