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Do you know how to generate *.pin file for my FPGA from Quartus II? This *.pin file will contain all pin assignments and also the voltage of each bank.
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I believe what you are asking is how to automate the pin assignments, so that you do not have to repeat it.
The solution is to use a Tcl script with the pin assignments. Take the design that you used to generate the *.pin file above (i.e., that file was generated when you synthesized that design). In the Quartus GUI select "Project->Generate Tcl file for Project" and look at the generated file. Inside that file you will see the Tcl statements that implement the pin assignments, and a lot more Tcl functions that setup the design.
Now, go and take a look at a few of the example designs I have posted, eg.,
Post#2
http://www.alteraforum.com/forum/showthread.php?t=45927 Post#20
http://www.alteraforum.com/forum/showthread.php?t=45748&page=2 Perform the steps in the readme.txt file, then use "Project->Generate Tcl file for Project" to generate a Tcl file, then go and take a look at constraints.tcl and synth.tcl. constraints.tcl contains the pin assignments and is reusable for any design that uses this board. synth.tcl is specific to a project and sets up the Quartus GUI.
Cheers,
Dave
Honored Contributor
