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Altera_Forum's avatar
Altera_Forum
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11 years ago

"gating" one process from another

Hi,

I am brand new to Verilog. I need to produce a specific bit stream output. The bit time is 0.5us so I have an Always block that executes every 0.5us and creates this bit stream. That is working ok. The problem is that the bit stream is continuous, back to back output. I need to gate it at a low frequency like 10Hz.

I tried creating another Always block that executes every 100ms and set/clears a flag that the Other Always block would read/clear. This does not work as variables cannot be operated on by separate Always blocks.

I am sure there is a fundamental solution, I just don't know the fundamentals. ;-)

Thanks

Rich

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Assuming you're operating from a single clock source, you could implement all of this in a single always block. However, there's nothing wrong with splitting logic up across more than one. This often helps readability.

    You can gate the output from block 1 with the control signal you're generating in block 2. A combinatorial statement should do the trick. This could reside in 3rd always block.

    Perhaps: 

    always @ (*)
    if (stream_active)                  // Control signal from always block 2, active every 100ms
        output_stream = stream_source;  // Whilst active, drive the output signal with the stream
    else
        output_stream = 0;              // Otherwise, turn it off

    Regards,

    Alex