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Altera_Forum's avatar
Altera_Forum
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16 years ago

gated clock implementation using altera standard scheme

I am trying to to implement a gated clock using the recommended scheme, but I keep getting a critical warning.

here is the warning:

Critical Warning: (Critical) Rule C101: Gated clock should be implemented according to the Altera standard scheme. Found 16 node(s) related to this rule.

Critical Warning: Node "SP:SP_1|SPCTL:SPCTL|SPCLK:SPCLK|cg_icg:RXXAOUTWR1Hclk_drv|CLKOUT"

here is the code:

module cg_icg ( CLK, CLKEN, SE, CLKOUT );

// -- inputs --

input CLK; // Input Clock

input CLKEN; // Clock Enable

input SE; // Scan Enable

// -- outputs --

output CLKOUT; // Gated output Clock

// -- wires --

wire cken; // Final Clock Enable

// -- regs --

reg clken2f; // Latched Clock Enable (2f signal)

assign cken = CLKEN | SE ;

always @ (posedge CLK or cken)

if(!CLK) clken2f <= cken;

assign CLKOUT = clken2f & CLK;

endmodule // cg_icg

Any suggestions ? Thanks in advance....

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    That's the Altera suggested scheme: 

    always @ (negedge CLK)
  clken2f <= cken;
assign CLKOUT = clken2f & CLK;
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    I believe the problem is that you did not negate the clock input to the register.

    Your always statement should be:

    --- Quote Start ---

    always @(negedge CLK)

    --- Quote End ---

    remove the (or cken)

    If you right click on the warning message and click "Help" you get some useful info:

    --- Quote Start ---

    If the combinational logic uses an AND gate, the clock port of the register that drives the AND gate should be active on the falling edge and the clock port of the register driven by the AND gate should be active on the rising edge.

    or

    If the combinational logic uses an OR gate, the clock port of the register that drives the OR gate should be active on the rising edge and the clock port of the register driven by the OR gate should be active on the falling edge.

    --- Quote End ---

    Jake